20
LTC1968
1968f
V
OUT
= ((5mV AC)
2
+ (0.4mV DC)
2
) " 1.001 + 0.2mV
= 5.221mV
= 5mV + 4.42%
As can be seen, the gain term dominates with large inputs,
while the offset terms become significant with smaller
inputs. In fact, 5mV is the minimum RMS level needed to
keep the LTC1968 calculation core functioning normally,
so this represents the worst-case of usable input levels.
Using the worst-case values of the LTC1968 static errors,
the total conversion error is:
V
OUT
= ((500mV AC)
2
+ (1.5mV DC)
2
) " 1.003 + 0.75mV
= 502.25mV
= 500mV + 0.45%
V
OUT
= ((50mV AC)
2
+ (1.5mV DC)
2
) " 1.003 + 0.75mV
= 50.923mV
= 50mV + 1.85%
V
OUT
= ((5mV AC)
2
+ (1.5mV DC)
2
) " 1.003 + 0.75mV
= 5.986mV
= 5mV + 19.7%
These static error terms are in addition to dynamic error
terms that depend on the input signal. See the Design
Cookbook for a discussion of the DC conversion error with
low frequency AC inputs. The LTC1968 bandwidth limita-
tions cause additional errors with high frequency inputs.
Another dynamic error is due to crest factor. The LTC1968
performance versus crest factor is shown in the Typical
Performance Characteristics.
Output Errors Versus Frequency
As mentioned in the design cookbook, the LTC1968 per-
forms very well with low frequency and very low frequency
inputs, provided a large enough averaging capacitor is used.
However, the LTC1968 will have additional dynamic errors
as the input frequency is increased. The LTC1968 is de-
signed for high accuracy RMS-to-DC conversion of sig-
nals up to 100kHz. However, the switched capacitor cir-
cuitry samples the inputs at a modest 2MHz nominal. The
response versus frequency is depicted in the Typical Per-
formance Characteristics titled Input Signal Bandwidth.
APPLICATIO S I FOR ATIO
U
U
U
Although there is a pattern to the response versus fre-
quency that repeats every sample frequency, the errors
are not overwhelming. This is because LTC1968 RMS
calculation is inherently wideband, operating properly with
minimal oversampling, or even undersampling, using sev-
eral proprietary techniques to exploit the fact that the RMS
value of an aliased signal is the same as the RMS value of
the original signal. However, a fundamental feature of the
?modulator is that sample estimation noise is shaped
such that minimal noise occurs with input frequencies
much less than the sampling frequency, but such noise
peaks when input frequency reaches half the sampling
frequency. Fortunately the LTC1968 output averaging fil-
ter greatly reduces this error, but the RMS-to-DC topology
frequency shifts the noise to low (baseband) frequencies.
See Output Noise vs Input Frequency in the Typical Perfor-
mance Characteristics.
Input Impedance
The LTC1968 true RMS-to-DC converter utilizes a 0.8pF
capacitor to sample the input at a nominal 2MHz sample
frequency. This accounts for the 1.2M& input impedance.
See Figure 20 for the equivalent analog input circuit. Note
however, that the 1.2M& input impedance does not di-
rectly affect the input sampling accuracy. For instance, if
a 15.5k source resistance is used to drive the LTC1968, the
sampling action of the input stage will drag down the
voltage seen at the input pins with small spikes at every
sample clock edge as the sample capacitor is connected to
be charged. The time constant of this combination is
small, 0.8pF " 15.5k& = 12.5ns, and during the 125ns
period devoted to sampling, ten time constants elapse.
Figure 20. LTC1968 Equivalent Analog Input Circuit
IN1
V
DD
V
DD
V
SS
V
SS
R
SW
(TYP)
2k
C
EQ
0.8pF
(TYP)
C
EQ
0.8pF
(TYP)
I
IN1
IN2
I
IN2
1968 F20
R
SW
(TYP)
2k
IIN
V V
R
IIN
V V
R
R
M
AVG
IN IN
EQ
AVG
IN IN
EQ
EQ
1
2
1.2
1 2
2 1
( )
=
( )
=
=
&
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